In order to improve the density of the memory device, the industry has worked extensively at developing a method for reducing the size of a two-dimensional arrangement of memory cells. As the size of the memory cells of the two-dimensional (2D) memory devices continues to shrink, signal conflict and interference will increase so significantly that it is difficult to perform operation of multi-level cell (MLC). In order to overcome the limitations of 2D memory device, the industry has developed a memory device having a three-dimensional (3D) structure to improve the integration density by way of arranging the memory cells three-dimensionally on the substrate.
One of the common 3D memory device structures used in current industry is terabit cell array transistor (TCAT). Specifically, a multilayer laminated structure (e.g., a plurality of ONO structures of alternating oxide and nitride) may firstly deposited on the substrate; etching the multilayer laminated structure on the substrate by an anisotropic etching process, a plurality of channel through-holes distributed along the extending direction of the word line (WL) of memory cell and perpendicular to the substrate surface are formed (may extend through to the substrate surface or with a certain over-etch); a plurality of pillar-shaped channels are formed by depositing materials such as polysilicon etc. in the channel through-holes; the multilayer laminated structure is etched along the WL direction to form a plurality of trenches extending through to the substrate, exposing the multilayer stack surrounding the pillar-shaped channels; considering the etching selectivity of adjacent layers in the stack, using the etching solution with relatively greater ratio of etching selectivity to remove the second type of material in the stack by wet etching, leaving a plurality of projecting structures made of the first type of material laterally distributed around the pillar-shaped channels; a gate dielectric layer made of high-k dielectric materials and a gate stack structure composed of metal gate conductive layers are deposited on sidewalls of the projecting structures in the trenches; the laminated structure is etched to form a plurality of source/drain contacts, and the rear end of the manufacturing process is completed. Here, a portion of projecting structures of the laminated structure leaving on the sidewall of pillar-shaped channels forms a plurality of spacers between the gate electrodes, leaving the gate stacks sandwiched between the spacers as control electrodes. When a voltage is applied to the gates, the fringe field of the gate will enable a plurality of source and drain regions to be induced on sidewalls of pillar-shaped channels made of e.g. polysilicon material, thereby constituting a gate array composed of a plurality of flash memory cells series-parallel coupled to record the stored logic states. Wherein, in order to extract the signals of a plurality of MOSFETs series-parallel coupled in the cell region, the drain regions are formed by deposition filling the top of the pillar-shaped channel with polycrystalline silicon material, and the metal contact plugs electrically connected to the drain regions are also formed to establish further electrical connection to the bit-line (BL) thereon. In addition, a common source region containing metal silicide contacts is formed in the substrate between a plurality of vertical pillar-shaped channels. Under the conductive condition of the cell, the current flows from the common source region to the vertical channel region around, upwardly passes through a plurality of induced source and drain regions induced in the vertical channel under the influence of the control voltage applied on the control gate (connected to the word line), and further flows to the bit-line thereon through the drain region on the top of the channel.
The TCAT device structure has many advantages such as body-erase (adjusting the control gate can cause change of the electric potential in the induced source/drain regions and the floating gate, which can be erased in its entirety) and metal gate (it can be more convenient to adjust the transistor threshold through controlling the work function of the metal material) and so on. However, on the other hand, since that all the gate and word line (WL) connections are shared link through etching holes, except the top select transistor (USG, located above the memory transistor cell strings), and the gate-last process is used for etching to remove a dummy gate and form a gate opening as well as deposit a metal gate, such deep contact hole and gate opening with extremely high aspect ratio (AR, for example, typically greater than 40:1 and even 100:1) will have increasing width due to the deposition of the multilayer films, thereby the density of the TCAT memory cell cannot be further reduce effectively. Meanwhile, the etching for both of the deep trenches and the deep hole channels are etching for multilayer stack, with great process complexity, and the shape difference from deep holes to deep trenches requires the change of the etching processes.
Compared to the TCAT technology, another common device structure is for example NAND configuration using the BiCS (bit cost can be reduced), the integration density is improved by disposing the memory cells on the substrate three-dimensionally, wherein the channel layer is vertically erected on the substrate, the gate is divided into three parts, namely a lower selection gate layer, a middle control gate layer and an upper selection gate layer, the crosstalk between signals can be reduced by distributing the gate signals into three groups of the gate electrodes. Specifically, the devices in the top and bottom layer are used as select transistors—vertical MOSFET with larger gate height/thickness, the gate dielectric layer is a single layer of conventional high-k material; the devices in the middle layer are used as a memory cell string, with smaller gate height/thickness, the gate dielectric layer has stack structure composed of a tunneling layer, a storage layer and a barrier layer. The specific manufacturing processes of the device with the BiCS-based NIND structure generally include, depositing the lower selection gate electrode layer on a silicon substrate, etching the lower selection gate electrode layer to form trenches through to the substrate for further deposition of the lower portion of channel layer and the lead-out contact of the lower gate electrode, depositing the control gate layer over the lower selection gate electrode layer, etching the control gate layer to form an intermediate channel region used for memory cell region and to create the lead-out contact for the middle control gate electrode, etching the control gate, dividing the whole device into a plurality of regions according to the word- and bit-line dividing requirements, depositing the upper selection gate layer over the control gate layer and etching it, depositing to form the upper channel and the upper lead-out contact, then completing the device fabrication through the subsequent processes. In the BiCS structure, except for the top select transistor USG, all of the gate electrodes beneath can be flat-shaped, which can avoid the contact process for deep trenches and deep holes for the TCAT, leading to the improvement of the memory density. In such process, the most critical etching step is merely the lithography of memory channel region and lead-out contact in the intermediate layer, which directly determines the integration density and signal anti-jamming capability of the whole device. However, although the BiCS structure can respectively use the control gate threshold through the stacked placement of the storage array and select transistors, also can avoid the complex process of the contact holes or gate openings with too large aspect ratio through the stratification of gate connections, it can only do erasing by polysilicon gate induced drain-leaked current (GIDL), without capability of body-erase, which results in low read-write efficiency.